Hybrid Memristor-CMOS computer for AI: From device to system
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Continued improvements in computing hardware performance become increasingly more challenging with the slowing down of the Moore’s law and fundamental limitations of the von-Neumann bottleneck. Recently, memristors and memristor crossbars have been extensively studied as promising candidates for next generation memory and computing applications due to the high storage density and superior performance metrics. In this thesis, I will discuss memristor device characteristics, modeling, and directly integrated hybrid memristor/CMOS systems for neuromorphic computing applications.
An accurate dynamic memristor switching model that can quantitatively explain Forming, sustained Set/Reset cycles, and multi-level storage will be discussed. Two different filament growth processes are captured by the model and verified by experimental DC and pulse measurements. Linear conductance updates and high on/off are observed in the bulk-type doping mode. Following individual device analysis, an integrated memristor/CMOS system consisting of a 54×108 passive memristor crossbar array directly fabricated on a CMOS chip will be presented. The system includes all necessary analogue/digital circuitry, buses, and a programmable processor to control the digital and analogue components to form a complete hardware system to perform vector matrix multiplication (VMM) functions in-memory and in parallel. Mapping of several networks is achieved in the prototype system, and larger networks can be mapped in a tiled architecture.
Chair: Professor Wei D. Lu