Yield Enhancement through Pre- and Post-Silicon Adaptation
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Achieving high parametric yield is always a key design objective. However, circuits designed in aggressively scaled technologies face more stringent design constraints and increased process variability. Traditional guard-band design methodologies that assume worst-case environmental factors and minimum feature size may reach overly conservative decisions with significant area/performance/power cost, and inevitably deteriorate the yield. Hence, design for yield in nano-meter regime has become highly imperative for chip designers. In this thesis, we focus on parametric yield enhancement when considering the process and environmental variability. We propose several pre- and post-silicon adaptation techniques which aim at solving a few key problems for yield enhancement, including: (1) pre-silicon optimization technique that clusters the gates and selects body bias at design stage to handle the complicated power-performance correlation; (2) post-silicon optimization technique that manages the trade-off between oxide breakdown reliability and chip performance with limited post-fabrication on-chip measurements. This post-silicon method helps designers tightly bound the chip reliability by considering the process variation and hence enables the use of available margin to boost the system performance while meeting the design lifetime. (3) the coordination of pre- and post-silicon optimization that aims at reducing the repeated optimization for the same design target by exploring the underlying relationship of pre- and post silicon techniques. (4) process variation modeling which is always a key problem for any yield enhancement technique. Unlike the traditional design time model constructed by measuring hundreds of testing wafers, the proposed framework can dynamically extract the variation from wafer to wafer and make the process model evolve by reusing information from past wafers to validate and improve the model.