Faculty Candidate Seminar
Toward Introspective and Adaptive system Architectures
Add to Google Calendar
Dr. Rabbah is from MIT
lThe performance gap between processor and memory has widened continuously over the last decade. As emerging multicore architectures are packing even more computational power onto a single chip, the memory bottleneck is becoming a central obstacle to achieving scalability. Such architectures generally magnify long memory access latencies, and require locality aware and latency hiding techniques to prevent the memory system from becoming a severe performance bottleneck.
This talk will describe a simple and effective methodology for mitigating the memory bottleneck. The strategy leverages speculative and predicated execution, and is readily applicable to commercial processors available today. In this work, the compiler uses cache-miss profiling to focus on a relatively small set of delinquent program references that suffer expensive cache misses. The compiler then automatically embeds new instructions into the host program to orchestrate runtime data management. The new instructions execute as part of the same instruction stream as their host, but effectively run ahead to carry out various optimizations that improve the overall performance. This talk will focus on data prefetching as one such optimization. In an implementation for the Itanium Processor Family, the optimization led to 30% faster execution, with an average 45% reduction in memory stalls. A significant aspect of this work is its ability to dynamically adapt to runtime information and dynamic behavior. For example, the compiler-embedded instructions self-nullify when they are likely to increase the burden on the memory system. The ability to dynamically change execution behavior marks a significant step toward autonomous, introspective, and adaptive applications.
Rodric Rabbah is involved in several projects as a Research Scientist at MIT. He is a leading contributor to StreamIt, a domain specific language and compiler for stream programming. He also leads the development of Reptile, an explicitly parallel compiler for tiled architectures. Currently, he is developing metrics to systematically categorize applications based on their runtime characteristics. This work culminates in VersaBench, a new benchmark suite intended to aid architects in the design of future microprocessors. Since 1999, he has led the development of the Trimaran VLIW processor simulator. Trimaran is an open-source compilation and simulation infrastructure for EPIC and VLIW research, and is used at more than thirty universities worldwide.