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Dissertation Defense

Machine Learning Meets Analog Circuit Design: Intelligent Automation of IC Design

Morteza Fayazi
1005 EECS BuildingMap
Morteza Fayazi Defense Photo



Analog and Mixed-Signal (AMS) circuits have broad-ranging applications across various fields, including wireless communication, biosensors, automotive systems, and more. However, one of the primary bottlenecks in supplying the current high-demand Integrated Circuits (ICs) with a short time to market is the manual design process. Manual circuit design is time-consuming and prone to human errors due to the extensive number of design parameters, the complexity of physical models, and severe process variations with the downscaling of technology nodes. Automating AMS circuit design has always been challenging, as it heavily relies on human expertise and intuition to establish relationships between various parameters and performance metrics. Therefore, there is a crucial need for autonomous AMS circuit design to catch up with the long-standing automation of digital circuits. Moreover, to achieve a fully no-human-in-the-loop IC design, it is essential to automate the integration of both AMS and digital blocks into a System-on-Chip (SoC).

  This talk explores novel ideas on infusing circuit design intuition into Machine Learning (ML) techniques to automate the circuit design process efficiently and intelligently. One of the main challenges in ML is obtaining robust and sufficient data for accurate modeling, especially given the high-dimensional variation space inherent in modeling the process variations and the costly simulations required for growing AMS systems. In the first part of the talk, we discuss approaches for AMS circuit design generation and Radio Frequency (RF) circuit modeling. The results show that our approaches require by up to 1090x less labeled data and our runtime is up to 75x faster than the state-of-the-art works. Subsequently, we delve into a fully automated Single-Board Computer (SBC) generator tool, which combines ML and data retrieval techniques to reduce the time needed for generating an SBC schematic from days to as little as two minutes.


CHAIR: Professor Ronald Dreslinski