Low-power interconnection networks

Systems from microprocessors to supercomputers, from embedded systems-on-a-chip to Internet routers are becoming increasingly interconnected, relying on network fabrics to scale up. With networks taking up a substantial portion of a system's limited power budget, it is now critical to explore low-power interconnection networks. In this talk, I'll first discuss the challenges faced as we move from high-performance networks, to networks that have to deliver the high performance requirements under tight power budgets. These challenges span fairly disparate areas, from theoretical analysis, to design tools, architectures as well as circuits. I'll briefly survey my group's research into each of these areas, before zooming in on several of the efforts, from theoretical power analysis, to network thermal modeling and management.
Li-Shiuan Peh has been an Assistant Professor of Electrical Engineering at Princeton University since 2002. She graduated with a Ph.D. in Computer Science from Stanford University in 2001, and a B.S. in Computer Science from the National University of Singapore in 1995. She is a recipient of the 2003 National Science Foundation's CAREER award and 2004's recipient of Princeton University's School of Engineering and Applied Sciences' E. Lawrence Keys/Emerson Electric Co. Faculty Advancement Award. She is the guest co-editor of the IEEE Transactions of Parallel and Distributed
Systems Special Issue on On-Chip Networks, and has been a program committee member on several conferences (HPCA, SIGMETRICS, Hot Interconnects, ICPP, HiPC, etc) and workshops (PACS, TACS, SAN, etc). Her research focuses on power-aware interconnection networks, on-chip networks and parallel computer architectures, and is funded by grants from the National Science Foundation, the DARPA MARCO Gigascale Systems Research Center and Intel Corporation.