High-Performance Process-in-Memory Architectures Design and Security Analysis

PASSCODE: 134D6F5

The performance of processor-centric von Neumann architectures is greatly hindered by data movement between memory and processor, especially when encountering data-intensive applications. Process-in-memory (PIM) architectures perform computation within the memory modules. Hence, the performance and energy penalty associated with data access can be mitigated by minimizing data movement and leveraging high internal bandwidth. Reducing memory access provides enhanced security resilience against bus-snoop attacks.

This dissertation proposes event-driven, cycle-accurate simulator design and implementation for PIM architectures based on dynamic random-access memory (DRAM) and resistive random-access memory (RRAM), along with how these simulators prompt PIM architecture development. This dissertation gives 1) system-level design configuration of RRAM-based analog PIM architecture for convolution neural networks inference; 2) DRAM-based PIM architecture for high performance and energy efficient GPT autoregressive token generation.

Two security investigations at side-channel leakage of RRAM-based analog PIM architectures will be analyzed by employing a dynamic power modeling approach. Vulnerabilities of 1) model extraction attack and 2) private input breach will be demonstrated. Countermeasures against these side-channel attacks will be discussed. To secure chips, a novel physical unclonable function (PUF) design will be covered.

CHAIR: Professor Wei Lu