High-Performance ADCs Using Floating Ring Amplifiers and Negative-C

High-performance ADCs are critical for a wide range of applications, including wireless communication, sensing, and data acquisition systems. As CMOS technology scales down, achieving high resolution, speed, and energy efficiency simultaneously has become increasingly challenging. This dissertation introduces advanced designs for high-performance ADCs, featuring floating ring amplifiers (FLORA) and Miller negative capacitance (Miller negative-C), to effectively overcome these limitations.

The first work introduces a SAR-assisted pipeline ADC using FLORA, which features bias-free and dynamic operation, optimizing power and pole placement through reservoir capacitors. Furthermore, Miller negative-C enhances the closed-loop gain accuracy without requiring additional correction circuitry, improving overall performance and power efficiency.

The second work introduces a noise-shaping SAR quantizer-based pipeline incremental ADC (IADC) incorporating a current-regulated FLORA (CURE FLORA) and a two-phase Miller negative-C. The pipeline IADC achieves a superior signal-to-quantization noise ratio with a low oversampling ratio. CURE FLORA leverages current regulation, along with offset-biasing and self-quenching, to reduce power consumption while maintaining high performance. Additionally, the two-phase Miller negative-C improves the accuracy of the switched-capacitor integrator, further enhancing the performance of the ADC.

The contributions of this dissertation address key challenges in ADC design, offering solutions for high performance, low power, and scalability in next-generation mixed-signal systems.

CHAIR: Michael P. Flynn