High-Integration, Programmable Wireless Interfaces for Long-Range Communications

The virtues of digital integrated circuits have been common knowledge for decades. Noise immunity and the ability to quickly scale existing digital solutions from one generation of silicon technology to the next are some of the advantages with performing electronic computation and communications in the digital domain. However, the world in which we live is still analog and some amount of analog/mixed-signal processing must take place to interface the analog world to digital electronics.
A highly integrated mobile wireless interface presents an environment which is excessively hostile to the analog portion of the radio channel. Common analog circuit figures of merit, such as dynamic range, linearity, and spurious noise performance with minimum power consumption will continue to make the wireless interface problem challenging from the perspective of understanding fundamental limits of modern silicon technologies to the realization of integrated mobile transceivers. Future wireless radios will continue to push the available range and bandwidth, allowing connectivity with any available RF standard for both short and long-range high bandwidth communication. The analog and mixed-signal techniques developed by exploring the wireless interface are typically extendable to a much broader class of mixed-signal interface problems in the areas of bioelectronics, MEMs interfaces, and wireline transceiver applications.
This presentation will discuss techniques to enhance the range of highly integrated mobile devices. Key components of a cellular transceiver, both transmit and receive, are illustrated. The devices, which were integrated in a CMOS technology, exploit the available digital logic to realize new calibration routines that enhance the performance in the analog domain. Specifically, methods to enhance range either through harmonic-rejection or manipulation of the various signal transfer functions within a phase-locked loop are discussed.
Jacques C. Rudell received a B.S. degree in electrical engineering from the University of Michigan, Ann Arbor. He later received a M.S.E.E. degree from the University of California, Berkeley, where he focused on high-speed, low-power digital-adaptive equalization techniques for magnetic disk-drive channels employing partial response signaling. He went on to receive his Ph.D. from UC Berkeley, completing his thesis and research on wireless transceiver architectures and systems suitable for high levels of integration in CMOS with multi-standard/modal operation capabilities.
From 1989 to 1991, he was an IC Designer and Project Manager with Delco Electronics (now Delphi), where his work focused mainly on bipolar analog circuits for automotive applications. From late 2000 to 2001, he was a postdoctoral Researcher at the University of California at Berkeley, in addition to holding consulting positions in several Silicon Valley firms. In early 2002, he joined Berkana Wireless, San Jose, CA as an Analog/RF IC Design Engineer. He currently is the Design Manager of Advanced IC Development exploring new transceivers systems in CMOS for a number of wireless applications.