Hardware and Software Design for 10 Gigabit Network Servers

As Internet link speeds grow to 10 Gigabits per second (Gbps) and beyond, network servers have the opportunity to utilize 10 Gbps Ethernet to connect to the Internet. However, modern CPUs and operating systems are not currently designed for the high frame rates of 10 Gbps Ethernet communication. This mismatch has motivated the design of network interface cards (NICs) that are capable of offloading storage and an evolving computational workload from the main host. Such NICs must be scalable, programmable, and meet the power constraints of a server peripheral device.

The work of my research group focuses on the design and simulation of network interface architectures, software for programmable network interfaces, and host operating system support for high-speed network servers. This talk will focus on our scalable Ethernet network interface controller architecture for 10 Gigabit network servers. The controller utilizes a partitioned memory architecture, parallel processing cores, a concurrent event-queue software mechanism, and application-targeted ISA extensions to achieve line rates on bidirectional streams of maximum-sized Ethernet frames. A simulated controller based on this architecture with six 170 MHz processing cores, a 4-way banked scratch-pad, and two 32-bit 500 MHz GDDR SDRAMs can achieve 99% of the theoretical peak bandwidth while also consuming substantially less processor power than a single-core solution.

Vijay S. Pai received a BSEE degree in 1994, an MS degree in 1997, and a Ph.D. degree in 2000, all from the Rice University Department of Electrical and Computer Engineering. He was a senior developer at iMimic Networking from 1999-2001 and an Assistant Professor at Rice University from 2001-2004. He joined the faculty of Purdue University in September 2004. Vijay's research interests include computer architecture, networking software, and performance evaluation. He received the NSF CAREER award in 2003.