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Systems Seminar - CSE

Hardware Acceleration and associated Algorithms for Packet searches

Srinivasan Venkatachary

High speed packet header processing has been an important area of research. Scalable solutions for high speed packet classification and forwarding table lookups are essential components of multi gigabit line-cards (10 Gbps – 80 Gbps). This talk is focused on the state-of-the art in specialty networking chipsets and associated algorithms for solving the classification and forwarding lookup problems. Specifically, Ternary Content Addressable Memories (TCAMs) have gained widespread acceptance as the de-facto solution for Access Control List (ACL) processing. This talk describes the state-of-the art in TCAM technology, and the challenges facing next generation TCAMs. Then, advanced algorithms for supporting 'ranges' in TCAMs are discussed. On scalable routing tables, an algorithmic solution for storing large (1M+) virtual routing tables on a single chip called 'sahasra' is discussed. Finally, work-in-progress on packet content search algorithms and approaches to hardware acceleration of content search such as for virus signature matching and Layer7 processing are discussed.
Srinivasan Venkatachary currently works at Cypress Semiconductor as Principal Architect. He holds several patents on scalable packet search algorithms and design of acceleration hardware. He was founder and chief scientist at Sahasra Networks, which was acquired by Cypress semiconductor. Prior to Sahasra Networks, he worked at Microsoft Research. Srinivasan obtained his PhD in computer science from Washington University, St. Louis in 1999.

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