Dissertation Defense

Geometric Partitioning for Parallelizing Post-Placement VLSI Design Processes

Name: Geometric Partitioning for Parallelizing Post-Placement VLSI Design Processes
Start: 2006-09-25T11:00:00-04:00
End: 2006-09-25T11:00:00-04:00

Jiyoun Kim

WHEN:

Monday, September 25, 2006 @ 11:00 am
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Dissertation Defense

Geometric Partitioning for Parallelizing Post-Placement VLSI Design Processes

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