Exploiting Reconfiguration and Co-Design for Domain-Agnostic Hardware Acceleration
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The end of classical semiconductor scaling has created strong demand for new hardware-software systems that can sustain future applications. Stringent requirements in power and performance make conventional compute (e.g., CPUs) impractical for a variety of domains. Thus, greater emphasis is placed on new hardware-software design paradigms, in particular on application-specific accelerators. Fixed-function accelerators can obtain power and performance orders of magnitude better than general-purpose counterparts, but such designs are typically restricted to narrow applications; this leaves ample room for complementary designs that strike a different balance between efficiency and programmability. Nevertheless, conventional programmable accelerators exhibit structural overheads that reduce hardware efficiency. Developing performant code for such accelerators is also challenging, due to optImizations that are strongly coupled to microarchitectural details.
This dissertation explores the use of reconfigurability and hardware-software co-design to address the challenges above. The first work presents a simulation-based architectural study that introduces a novel, coarse-grained reconfigurable multi-core accelerator. Based on learnings from the former, we design a prototype Arm-based architecture, named Versa, that incorporates ASIC-like spatial data reuse, and architectural enhancements to exploit runtime algorithm properties. The third and final work explores the software-optimization challenges posed by emerging programmable designs. To support Versa and related spatial accelerators, we build an end-to-end compilation stack that leverages polyhedral techniques for fully-automatic generation of optimized parallel code.
Chair: Professor Ron G. Dreslinski