Enhancing Energy Efficiency in Intelligent Edge Systems through Hardware-Algorithm Co-design

With the rise of artificial intelligence (AI), enabling on-device intelligence for edge devices presents challenges due to high computational and memory demands. Hardware-algorithm co-design is essential to enhance energy efficiency in such resource-constrained environments. This dissertation introduces key techniques for efficient AI acceleration on edge devices in different scenarios.

First, a 22nm multi-modal signal processing SoC (AIMMI) is designed, delivering efficient audio, image, and cross-modal processing. AIMMI achieves high energy efficiency through dynamic power gating of 2MB MRAM, multi-mode system-level power management, and optimized neural engine dataflows. Second, an efficient algorithm and architecture for multi-task NLP (TaskFusion) is designed, which reduces computational load through weight and activation sharing between tasks. A novel heterogeneous architecture featuring dense, sparse, and attention cores fully exploits inter-task delta sparsity. Finally, a 22nm multi-task Transformer acceleration SoC (MITTA) with mixed-precision structured sparsity and hierarchical task-adaptive DVFS is designed to accelerate multi-task image and NLP processing. These contributions highlight the power of co-optimization of algorithms, architectures, and circuits to achieve highly energy-efficient edge AI systems.

CHAIR: Professor Dennis Sylvester