Design of Clock Distribution in High Performance Processors

The design of the clock distribution networks that provide a clock with low skew and jitter to the flip-flops and latches in all regions of the die in a high performance microprocessor has been a major challenge for the circuit designer in each new generation. This talk will describe the evolution in the design of clock generators and clock distribution networks over the many generations of Intel microprocessors beginning with the 50MHz Intel 80486, and going through to the 3.0 GHz Pentium 4 and the Core 2 Duo architectures. The process technology challenges and network topologies enabling the design of low skew and jitter clock networks will be presented. The methods with which microprocessor circuit designers have used PLLs for the I/O clocking will also be described.
Ian Young received the BSEE and the M. Eng. Science from the University of Melbourne, Australia. He received the Ph.D in Electrical Engineering from the University of California, Berkeley, where he was one of the pioneers of the switched capacitor filter in MOS technology.

In 1983 he joined Intel Corporation, in the Portland Technology Development group. He is now an Intel Senior Fellow and Director of Advanced Circuits and Technology Integration in the Technology and Manufacturing Group. His technical contributions at Intel have been in the design of DRAMs and SRAMs, microprocessor circuit design, the design of Phase Locked Loops for microprocessor clocking and high speed I/O links, mixed-signal analog and RF CMOS circuits for wireless and wireline communications products. He has also contributed to the definition and development of most of the process technology generations for Intel’s microprocessor and communications products since the 1.0um 2-layer metal CMOS generation.

He is an IEEE Fellow