Design for Manufacturing effects in the nano-scale era

This talk focuses on physical design for manufacturability issues, and how they might impact digital design and models. This is based on experiences with TI 90 and 65nm digital standard cell libraries. A mix of chip level, cell level and transistor level topics are covered. This is based on an internal TI training course and tutorial at ISSCC05 microprocessor tutorial.
Clive Bittlestone is Architecture Manager at the Backplane Technology Center of Texas Instruments. He is a TI Fellow. Clive is the Architect of most of TIs ASIC Standard Cell Libraries for the past 9 technology nodes. He is currently working on 45nm Standard Cell Architecture. His research interests are Statistical design, Asynchronous design, Open Standards, Open Source Software and Open Hardware.