Combining Circuits + Architecture to Combat Variability in Nanoscale CMOS

Variability is poised to severely degrade performance and power scalability of circuits and systems in nanoscale CMOS technologies. Process, voltage, and temperature variations are well-known effects that occur across wide temporal and spatial scales. With aggressive technology scaling, traditional worst-case design techniques incur large overheads. Higher-level solutions, combined with innovations at the circuit level, offer a holistic approach that should combat and mitigate the detrimental effects of variability. This talk presents a broad perspective of how we leverage collaborations between circuits and architecture to address variability in different contexts. Random and systematic variation can introduce skew between clock phases in a high-speed interleaved transmitter. Instead of applying circuit-level patches, we treat offsets as a form of internal inter-symbol interference (ISI) and show how a look-up table (LUT) based equalizer can compensate for internal clock timing and transmitter current mismatch to improve signal integrity. In addition to mixed-signal transceiver blocks, process variation can degrade power and performance of digital systems. This talk introduces ReVIVaL, which incorporates two techniques to combat variability—voltage interpolation and variable latency. When applied to a 6-stage floating-point unit (FPU), experimental results from a 130nm test chip demonstrate how these techniques can compensate for random and correlated device-level variations without compromising performance. We also explore the potential benefits of ReVIVaL extended to a CMP system. Besides process variation, voltage variation can also degrade performance scalability and require power overheads. Hence, we investigate the potential energy savings offered by temporally fine-grained, per-core DVFS using integrated on-chip switching regulators. Our analysis suggests energy savings are possible through fast, per-core DVFS despite the overheads associated with lower-effiency on-chip regulators. Finally, I will summarize other research efforts we have on-going at Harvard.

Gu-Yeon Wei joined Harvard University in January 2002 and is currently an Associate Professor of Electrical Engineering. Prior to joining Harvard, he spent 18 months at Accelerant Networks in Beaverton, Oregon. Professor Wei received his BS, MS, and PhD degrees in Electrical Engineering all from Stanford University in 1994, 1997, and 2001. His current research interests are in the areas of mixed-signal VLSI circuits and systems design for high-speed/low-power wireline data communication, energy-efficient computing devices for sensor networks, and collaborative software + architecture + circuit techniques to overcome variability in nanoscale IC technologies.