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Dissertation Defense

Circuits & Techniques for Cell-based Analog Design Automation of Low Dropout Regulators

Yaswanth Kumar Cherivirala
1303 EECS BuildingMap

Advances in CMOS based semiconductor fabrication and lithography techniques lead to increased short channel effects, low breakdown voltages of FETs and an exponential increase in layout constraints, making the manual circuit design and layout a less robust and time intensive process. While digital CAD tools can automatically synthesize and implement a digital design, analog circuit design and layout generation remains a significant bottleneck for automating the design of complete system on chips (SoCs). This thesis presents a low dropout regulator (LDO) generator tool that can automatically output a LDO design based on user specified performance requirements in a given process design kit (PDK).

Using an array of current switches that can be controlled using digital controllers as the baseline for voltage regulation, the presented LDO generator can automatically choose between three different digital controller architectures. DC specifications (input/output voltages, maximum load current & dropout) are synthesized using the I-only architecture. Transient specifications (maximum undershoot/overshoot, minimum transient time & output capacitance) are synthesized using the PI-controller architecture. To further improve the transient performance and the range of transient specifications that can be synthesized, a novel synthesizable PID controller has been demonstrated in this work. Furthermore, a hybrid LDO architecture with integrated analog control loop is proposed to enhance the PSRR performance of the LDO and realize a universal LDO architecture. The LDO generator is demonstrated and tested in multiple technology nodes signifying the robustness and practical application of the generator.


Chair: Prof. David D. Wentzloff