Circuits and Techniques for Digital Frequency Synthesizers and Design Automation.

Clock generator circuits have been extensively explored in the area of design automation due to the digital nature of clock signal and early development of all-digital architectures. But prior arts showed limits in two areas: 1) fully automating the design process starting from a user given specification, 2) systematic solution to alleviate the degradation of analog performance due to the automatic routing and noisy ring-oscillator.

First part of this thesis presentation proposes a design automation flow for baseline ADPLL architecture. By combining physics based equation and simulation results, we show a sample efficient modeling method that successfully predicts key metrics of ring-oscillator with high accuracy. The PLL generator outputs a GDS file from input specification within 2 hours, supporting three process nodes.

The second part of this presentation analyzes PLL fractional spur’s impact on Bluetooth low energy (BLE) spectrum and defines spectral mask for PLL. Also, we propose a novel two-step TDC architecture and calibration scheme to overcome the performance limits coming from random routings.

Final part of the presentation proposes an all-digital fractional-N multiplying delay-locked loop that uses reference triggered ring oscillator as a coarse DTC that reduces fine DTC range by 9x while achieving aggressive oscillator noise suppression.

Chair: David Wentzloff