Challenges in Integration of Nanoscale Technology and VLSI Design
Mr. Sunit Rikhi
Director of Advance Design
Logic Technology Development
Thirty-eight years after "moore's law" was introduced, it continues to drive the scaling of transistors with large VLSI designs approaching a billion transistors on a single chip. We are now in the nanoscale regime with growing challenges in design-process technology integration during their concurrent development phase. It has become increasingly difficult to print physical layout of complex circuits on real silicon. Product design requires sophisticated modeling tools and flows in accurately predicting many physical effects during translation of design on the silicon. This talk will provide a broad overview of such complexities in a variety of areas including: technology mandated product layout rules; Optical Proximity Correction (OPC), statistical modeling of circuit behavior for process induced variations and the increasingly significant role of design collateral developed during process technology development.
Sunit Rikhi is Director of Advanced Design in Logic Technology Development located in Hillsboro, Oregon. His organization delivers capabilities to optimize and integrate Intel's logic and communications product designs with leading edge silicon process technologies. These include, process design rules, optical proximity correction of layout, tapeout process development, technology learning vehicles including SRAM structures, Standard cell libraries and a wide range of design collaterals validated in silicon during process development.
Rikhi joined Intel in 1984 as a Senior CAD engineer and developed an internal layout verification and extraction system. He received an Intel achievement award for this work in 1986. Since then, Sunit has held a variety of senior engineering management positions in Intel's Mask Operations and in Logic Technology Development. Before joining his current position in 2002, Rikhi lead the development of Intel's process technology automation for 300mm fully automated wafer fabs.
Rikhi is a graduate of University of Washington (MSEE, 1981) and BITS Pilani, India (BSEE, 1979)