Carbon Nanotube Electronics: Modeling, Circuit Implications, and Challenges

In an attempt to alleviate the problems associated with the scaling of silicon transistors, researchers have began a quest for novel alternate materials in a post-Si nanoelectronics era. Of the different materials investigated, carbon nanotubes with their superior transport properties, excellent thermal conductivities and high current handling capacities have proved to be a potential heir to Si. For circuit and system designers, the question at hand is how to use these “supertubes” in digital computation. In this talk I will discuss our work on carbon nanotube based electronics both for high performance VLSI as well as for ultralow power designs. I will present the circuit compatible physical models and detailed Non Equilibrium Green’s Function based numerical models that we have developed for Schottky barrier and MOS carbon nanotube FETs, and also a methodology to use this models for estimating circuit/system level power-performance trade-offs. The different flavors of nanotubes, their potential fields of application and implication on sustaining Moore’s law will be discussed. We have developed a simulation platform to study the impact of variation on nanotube FETs and I will share some of the key insights that can be obtained from it. It helps us identify the major technological barriers that must be overcome before carbon nanotube electronics is commercially viable.
Arijit Raychowdhury received his B.E. in 2001 from Calcutta, India and his PhD in 2006 from Purdue University, IN. He has worked as an Analog Circuit Designer with Texas Instruments Incorporated, Dallas (2002 to 2003) and with the Circuit Research Labs, Intel Corporation (summer of 2005 and 2006) pursuing design ideas with novel nanodevices. Presently he is working in the Microprocessor Technology Lab in Intel Corporation on novel sensor circuits and resilient circuit techniques.

His research interests include device/circuit design for scaled silicon and nonsilicon technologies. He holds eight patents and has published over forty articles in journals and refereed conferences. Dr. Raychowdhury received the Meissner Fellowship from Purdue University in 2002, the NASA INAC Fellowship in 2003, and the Intel Ph.D. Fellowship Award in 2005. He has received Best Paper Awards at IEEE NANO 2003 and International Symposium of Low Power Electronic Design (ISLPED) 2006. He has received the 2007 Dimitri N. Chorafas Award for the best dissertation in the College on Engineering, Purdue University.